In a communication system using a W-CDMA (Wideband Code Division Multiple Access) communication method, at the time of communication through an uplink from a mobile station to a base station, an HPSK (Hybrid Phase Shift Keying) modulator is employed to achieve modulation of signals.
One example of configurations of the HPSK modulator is shown in FIG. 7. The HPSK modulator is set forth in Technical Specification 3GPP (3rd Generation Partnership Project) TS 25.213 of 3GPP being a standard specification of mobile communication system.
In FIG. 7, data to be transmitted via a plurality of signal channels are shown as each of DPDCH1 (Dedicated Physical Data Channel 1) data to DPDCH6 data, DPCCH (Dedicated Physical Control Channel) data, and HS-DPCCH (High Speed DPCCH) data. Each piece of data is one-bit time-series data. The modulator is provided with a plurality of multipliers 901 to 908 and a plurality of multipliers 910 to 917 and each of the plurality of multipliers 901 to 908 and of multipliers 910 to 917 corresponds to each of the channels. Each piece of the data DPDCH1 to data DPDCH6, data DPCCH, and data HS-DPCCH is multiplied, for channel multiplexing, by each of channelization codes Cd1 to Cd6, Cc, and Chs each being one-bit time-series data to be used for channel identification in each of the multipliers 901 to 908. Next, in each of the multipliers 910 to 917, each piece of the data DPDCH1 to data DPDCH6, data DPCCH, and data HS-DPCCH is multiplied, for level setting to every channel, by each of gain factors βd1 to βd6, βc, and βhs. Each of the gain factors βd1 to βd6, βc, and βhs is time-series data consisting of a plurality of bits in width. Therefore, each of outputs from the multipliers 910 to 917 is also time-series data consisting of a plurality of bits in width.
In the examples in FIG. 7, the outputs from the multipliers 910 to 917 are grouped into data for an in-phase channel and data for an orthogonal channel and each of the outputs from the multipliers 910 to 913 is inputted, as a real number, to an in-phase channel adder 919 for adding operations and each of the outputs from the multipliers 914 to 917 is inputted, as a real number, to an orthogonal channel adder 920 for adding operations. A real number output I from the in-phase channel adder 919 and a real number output Q from the orthogonal channel adder 920 are inputted to a complex-number computing section 930. The complex-number computing section 930 includes a complex-number multiplier 921, a complex-number multiplier 922, and a complex-number adder 923.
In the complex-number computing section 930, the output Q from the orthogonal channel adder 920 is multiplied by an imaginary unit “j” in the complex-number multiplier 922 and then the product is added to the output I from the in-phase channel adder 919 in the complex-number adder 923 and, thereafter, the output is handled as a complex-number signal (I+jQ). The complex-number signal (I+jQ) is multiplied by a scramble code (Si+jSq) being specific to a mobile station for identification of the mobile station in the complex-number multiplier 921 and, as a result, a complex-number signal (I′+jQ′) is generated. The scramble code (Si+jSq) is a complex number whose a real part is Si and whose coefficient of an imaginary part is Sq and each of the codes Si and Sq is one-bit time-series data. Its real part I′ is separated from the coefficient Q′ of its imaginary part and each is outputted, as a real number, from the complex-number computing section 930. After filtering is performed for restricting bandwidth and for providing roll-off characteristics on the complex-number signal (I′+jQ′) in each of raised-cosine filters 924 and 925 (hereinafter, in drawings, referred simply to as a “raised COS filter”), signals Iout and Qout are outputted therefrom.
An example of configurations of the raised cosine filter is showed in FIG. 8. As the raised cosine filter, in general, a FIR (Finite Impulse Response) filter is used.
The raised cosine filter is configured to impose restrictions on a transmitting frequency bandwidth by providing an input signal generally having a rectangular waveform with route roll-off characteristics, without causing intersymbol interference to a received demodulated signal, and to make up a matched filter together with filters mounted on a receiver side.
Hereinafter, in drawings, a symbol X(n) denotes n-th data in a data string X. A symbol “n” (integer number) denotes a time-series string and data having the larger “n” represents the later data in terms of time. In the W-CDMA communication method in particular, an oversampling operation is performed at a frequency obtained by multiplying a chip-rate frequency of 3.84 MHz used as a reference frequency by an integer and, here the “n” corresponds to discrete time.
As shown in FIG. 8, the raised cosine filter includes a shift register 801, a plurality of multipliers 802 to 805, a plurality of weighting coefficient generators 806 to 809 (in FIG. 8, shown as “T0”, “T1”, . . . , “Tm−2”, “Tm−1”) and an adder 810.
The data X(n) is inputted to an m-bit (“m” being an integer) shift register 801. At this time point, the shift register 801 simultaneously outputs data X(n), X(n−1), . . . , X(n−m+2), X(n−m+1). The data X(n), X(n−1), . . . , X(n−m+2), X(n−m+1) is input respectively to the multipliers 802 to 805 and is multiplied respectively by weighting coefficients T(0), T(1), . . . , T(m−2), T(m−1) in the multipliers 802 to 805, and then is added in the adder 801 for being outputted. The weighting coefficients T(0), T(1), . . . , T(m−2), T(m−1) are respectively generated by the weighting coefficient generators 806 to 809.
Time-series operations of the HPSK modulator are described by referring to FIGS. 8 and 9. Here, for simplification, cases are shown in which the in-phase channel group shown in FIG. 7 includes only the DPDCH1 channel and the orthogonal channel group shown in FIG. 7 includes only the DPCCH channel.
DPDCH1 channel data D(n) is multiplied by a channelization code Cd (n) in the multiplier 701 and the product is further multiplied by a gain factorβ d(n) in the multiplier 703 and the product becomes in-phase input data I(n) of the complex-number computing section 710. The data I(n) is shown by the following equation (1).I(n)=D(n)·Cd(n)·βd(n)  (1)
DPCCH channel data C(n) is multiplied by the channelization code Cc (n) in the multiplier 702 and the product is further multiplied by a gain factorβ c(n) in the multiplier 704 and the product becomes orthogonal input data Q(n) of the complex-number computing section 710. The data Q(n) is shown by the following equation (2).Q(n)=C(n)·Cc(n)·βc(n)  (2)
The complex-number computing section 710, when having fetched the in-phase data I(n) and orthogonal input data Q(n), first multiplies the orthogonal input data Q(n) by an imaginary unit “j” by the multiplier 706 and then adds the product to the in-phase input data I(n) in the adder 707 to generate complex-number data (I(n)+jQ(n)). Complex-number data (I(n)+jQ(n)) is multiplied by a scramble code {Si(n)+jSq(n)} being complex-number data in the multiplier 705 to generate complex-number data (I′(n)+jQ′(n)). The complex-number data {I′(n) +jQ′(n)} is shown by the following equation (3).
                                                        I              ′                        ⁡                          (              n              )                                +                      j            ⁢                                                  ⁢                                          Q                ′                            ⁡                              (                n                )                                                    =                                            {                                                I                  ⁡                                      (                    n                    )                                                  +                                  j                  ⁢                                                                          ⁢                                      Q                    ⁡                                          (                      n                      )                                                                                  }                        ·                          {                                                Si                  ⁡                                      (                    n                    )                                                  +                                  j                  ⁢                                                                          ⁢                  S                  ⁢                                                                          ⁢                                      q                    ⁡                                          (                      n                      )                                                                                  }                                =                                    {                                                                    I                    ⁡                                          (                      n                      )                                                        ·                                      Si                    ⁡                                          (                      n                      )                                                                      -                                                      Q                    ⁡                                          (                      n                      )                                                        ·                                      Sq                    ⁡                                          (                      n                      )                                                                                  }                        +                          j              ⁢                              {                                                                            I                      ⁡                                              (                        n                        )                                                              ·                                          Sq                      ⁡                                              (                        n                        )                                                                              +                                                            Q                      ⁡                                              (                        n                        )                                                              ·                                          Si                      ⁡                                              (                        n                        )                                                                                            }                                                                        (        3        )            
The complex-number computing section 710 outputs the real part I′(n) of the complex number data {I′(n)+jQ′(n)} and the imaginary coefficient Q′(n) as real number data to each of the raised cosine filters 708 and 709. Since a real part and an imaginary part are independent from each other, in order to make the equation (3) hold all the time, the I′(n) and Q′(n) have to be given as the following equations (4) and (5).I′(n)=I(n)·Si(n)−Q(n)·Sq(n)  (4)Q′(n)=I(n)·Sq(n)+Q(n)·Si(n)  (5)
By substituting the equations (1) and (2) into the equations (4) and (5) respectively and rearranging the equations, the following equations (6) and (7) can be obtained.I′(n)={D(n)·Cd(n)·Si(n)}·βd(n)−{C(n)·Cc(n)·Sq(n)}·βc(n)  (6)Q′(n)={D(n)·Cd(n)·Sq(n)}·βd(n)+{C(n)·Cc(n)·Si(n)}·βc(n)  (7)
When the raised cosine filters 708 and 709 are made up of the FIR filter having the number of taps of “m” and weighting coefficients T0, T1, . . . , Tm−1, their outputs Iout(n) and Qout(n) are shown respectively by the following equations (8) and (9).Iout(n)=T0·I′(n)+T1·I′(n−1)+ . . . +Tm−2·I′(n−m+2)+Tm−1·I′(n−m+1)  (8)Qout(n)=T0·Q′(n)+T1·Q′(n−1)+ . . . +Tm−2·Q′(n−m+2)+Tm−1·Q′(n−m+1)  (9)
Each of the I′(n) and Q′(n) contains a gain factor as a factor of a product and, therefore, is data made up of a plurality of bits. Also, the weighting coefficient Tk (K=0, 1, . . . , m−1) is data consisting of a plurality of bits. As a result, according to the equations (8) and (9), in the computation by each of the raised cosine filters, multiplications among data consisting of a plurality of bits occur by the number of taps.
By substituting the equations (6) and (7) into the equations (8) and (9) respectively and rearranging these equations, the following equations (10) and (11) can be obtained.Iout(n)=T0·{βd(n)·D(n)·Cd(n)·Si(n)−βc(n)·C(n)·Cc(n)·Sq(n)}+T1·{βd(n−1)·D(n−1)·Cd(n−1)·Si(n−1)}−βc(n−1)·C(n−1)·Cc(n−1)·Sq(n−1)}+ . . . +Tm−2·{βd(n−m+2)·D(n−m+2)·Cd(n−m+2)·Si(n−m+2)−βc(n−m+2)·C(n−m+2)·Cc(n−m+2)·Sq(n−m+2)+Tm−1·{βd(n−m+1)·D(n−m+1)·Cd(n−m+1)·Si(n−m+1)−βc(n−m+1)·C(n−m+1)·Cc(n−m+1)·Sq(n−m+1)  (10)Qout(n)=T0·{βd(n)·D(n)·Cd(n)·Sq(n)+βc(n)·C(n)·Cc(n)·Si(n)}+T1·{βd(n−1)·D(n−1)·Cd(n−1)·Sq(n−1)}+βc(n−1)·C(n−1)·Cc(n−1)·Si(n−1)+ . . . Tm−2·{βd(n−m+2)·D(n−m+2)·Cd(n−m+2)·Sq(n−m+2)+βc(n−m+2)·C(n−m+2)·Cc(n−m+2)·Si(n−m+2)}+Tm−1·{βd(n−m+1)·D(n−m+1)·Cd(n−m+1)·Sq(n−m+1)}+βc(n−m+1)·C(n−m+1)·Cc(n−m+1)·Si(n−m+1)}  (11)
As a result, in the raised cosine filter described above, the multiplications among pluralities of bits occur the number of times being twice the product obtained by multiplying the number of taps of the FIR filter by a clock frequency (product of a chip-rate frequency and oversampling rate) per unit time, which causes an enormous amount of operations.
This presents problems in that a computing circuit becomes large in scale, causing difficulties in miniaturization and increased costs for a modulator. Also, power consumption to operate the circuit is increased, which causes an increase in heat generation. Another problems arise in that, when computing accuracy is to be made higher to improve signal quality, an amount of computation also increases, which makes the computing circuit further larger in scale and increases the consumption power, still further leading to difficulties in the improvement of signal quality.
Conventional technologies to solve the above problem are disclosed, for example, in Japanese Patent Application Laid-open Nos. 2001-339365 (Patent Reference 1) and 2001-156679 (Patent Reference 2). In the Patent References 1 and 2, technologies are disclosed which try to decrease an amount of computations by changing the sequence of computations through a contrivance.
Among data to be inputted for computations, data consisting of a plurality of bits are gain factors and weighting coefficients. Since inputted data other than that is one-bit data for which an exclusive OR circuit can be employed as a multiplier, the computing circuit can be made smaller in scale, thereby reducing power consumption. In the Patent References 1 and 2, the above problems are tried to be solved by shifting plural-bit multiplying computations toward the end of computing order.